1. Field of the Invention
This invention relates to flip-flop circuits and, more particularly, to flip-flop circuits having low power consumption, low latency, and low hold-time characteristics.
2. Description of the Related Art
Almost all modern microprocessors use a technique called pipelining to increase throughput. Pipelining involves partitioning a process with "n" steps into "n" hardware stages, each separated by memory elements called registers which hold intermediate results. These registers are typically implemented using flip-flop circuits. There is one pipeline stage for each step in the process. By allowing each of the "n" stages to operate concurrently, the pipelined process could theoretically operate at nearly "n" times the rate of the non-pipelined process.
The benefits of pipelining in a microprocessor may be diminished if the latencies associated with the inter-stage registers consume a sizable percentage of the period of the microprocessor's internal clock. The latency t.sub.DQ of a flip-flop circuit may be generally defined as t.sub.SU +t.sub.CQ, where t.sub.SU is the setup time and t.sub.CQ is the clock-to-valid output time. With ever-increasing clock frequencies, it is becoming increasingly important to implement inter-stage registers of microprocessors using flip-flop circuits with very low latencies.
Another important characteristic associated with the flip-flop circuits which form inter-stage registers in microprocessors is hold-time. The hold-time of a flip-flop circuit is defined as the minimum time the data input signal must be valid following a sampling clock edge. Violations in the hold-time of a flip-flop circuit may result in race conditions. Like latency, it is desirable to reduce the required hold-time characteristics of flip-flop circuits which are used to implement inter-state registers in microprocessors.
Several additional considerations may also be important in the designs of flip-flop circuits used in microprocessors. For example, it is often important to utilize flip-flop circuits which are associated with low-power consumption characteristics. Low-power consumption is particularly important for microprocessors utilized in mobile applications, such as in lap-top computers.
In addition, it is often desirable to embed logic functionality within the input section of a flip-flop circuit. However, in a typical flip-flop circuit, the addition of logic functionality at the input section creates difficulties since the symmetry in the flip-flop's differential input amplifier section may be lost. For example, a four-input NOR gating function provided on one side of the differential amplifier typically requires that a matching four-input NAND gating function be provided on the opposite side of the differential amplifier.
FIG. 1 is a schematic diagram illustrating a typical prior art flip-flop circuit. The flip-flop circuit of FIG. 1 includes a differential stage 10 coupled to a pair of cross-coupled NAND gates 12. The cross-coupled NAND gates 12 form an S-R latch. During operation, lines 14 and 16 of respective sides of differential stage 10 are precharged high when the clock signal CLK is low. When the clock signal CLK goes high, transistor 18 turns on, as well as one of transistors 20 or 22, depending upon the state of input signals INL and INH (which are differential in nature). This correspondingly causes one of lines 14 or 16 to be discharged low to Vss. One of the output lines OUTL or OUTH of the flip-flop circuit is accordingly driven to a high state, and the other output is driven to a low state. These values are held through the precharge phase of a subsequent clock cycle, and may be altered in accordance with a change in the input signal during a subsequent evaluation phase. It is noted that transitions from low to high in output signal OUTL (and corresponding transitions from high to low in output signal OUTH) are caused by discharging line 14 of differential stage 10, while transitions from low to high in output signal OUTH (and corresponding transitions from high to low in output signal OUTL) are caused by discharging line 16 of differential stage 10.
Implementations of the flip-flop circuit of FIG. 1 may be associated with relatively high latency and hold-time characteristics, as well as relatively high power consumption characteristics. This is due in part to the fact that both sides of the differential stage are used to control the state of the cross-coupled NAND gates 12, thus requiring that the transistors forming each side of differential stage 10 be of sufficient size to drive cross-coupled NAND gates 12.
It would be desirable to provide a flip-flop circuit which is associated with low power consumption, low latency, and low hold time characteristics. Additionally, it would be desirable to provide a flip-flop circuit which readily accommodates complex input logic.